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VLSI Design
Volume 13 (2001), Issue 1-4, Pages 453-458
http://dx.doi.org/10.1155/2001/70818

Simulation of Enhanced Interface Trapping Due to Carrier Dynamics in Warped Valence Bands in SiGe Devices

Nanoelectronics Research Centre, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, Scotland

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Much of the potential of SiGe for p-MOSFET application is reduced by the lower than expected hole mobilities which are likely to be lowered by interface roughness scattering. The present paper analyses a hitherto unrecognised enhancement of interface scattering and trapping process which arises from the complex hole dynamics in the warped heavy hole band.