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VLSI Design
Volume 12 (2001), Issue 4, Pages 537-549
http://dx.doi.org/10.1155/2001/87048

Random Pattern Testability Enhancement by Circuit Rewiring

1Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi 621, Taiwan
2School of Information Technology and Engineering, University of Ottawa, Ottawa, Ontario KIN 6N5, Canada
3Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH 45221, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation

Abstract

Generally, there exist random-pattern resistant faults that result in the poor fault coverage in Build-In Self-Testing (BIST) scheme. In this paper, we propose a method to enhance the random pattern testability by a circuit restructuring technique, called circuit rewiring. The basic idea of rewiring is to replace a wire by another wire with the circuit functionality remaining unchanged. For two types of rewiring, fanin rewiring and fanout rewiring, we first analyze the testability change for each type of wire replacement. Based on the analysis, an efficient algorithm is given to enhance circuit testability. For a poor observability node, we try to increase its observability by adding an additional fanout to the node and removing an alternative wire whose source node has relatively good observability. The technique does not introduce any hardware overhead and performance degradation since a wire addition is followed immediately by another wire removal. Thus, it is basically cost-free when compared to other testability enhancement techniques.