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VLSI Design
Volume 2007 (2007), Article ID 68432, 16 pages
doi:10.1155/2007/68432
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic
1Department of Electrical Engineering, Eindhoven University of Technology, MB Eindhoven 5600, The Netherlands
2Computer Engineering, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, GA Delft 2600, The Netherlands
3SOC Architectures and Infrastructure, Research, NXP Semiconductors, AE Eindhoven 5656, The Netherlands
Received 15 October 2006; Accepted 4 March 2007
Academic Editor: Davide Bertozzi
Copyright © 2007 Andreas Hansson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
One of the key steps in Network-on-Chip-based design is spatial mapping of cores
and routing of the communication between those cores. Known solutions to the mapping and
routing problems first map cores onto a topology and then route communication, using separate
and possibly conflicting objective functions. In this paper, we present a unified single-objective
algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main
contribution, we show how to couple path selection, mapping of cores, and
channel time-slot allocation to minimize the network required to meet the constraints of
the application. The time-complexity of UMARS+ is low and experimental results indicate
a run-time only