VLSI Design
Volume 2007 (2007), Article ID 95348, 17 pages
doi:10.1155/2007/95348
Research Article
Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh 15213-3890, PA, USA
Received 12 December 2006; Accepted 6 February 2007
Recommended by Maurizio Palesi
Abstract
As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design
and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of 100% correctness
for devices and interconnects drastically reduces the costs of design but, at the same time, requires
SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a
novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication
from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a
built-in tolerance to DSM failures, without a significant performance penalty. By using this communication
scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization
failures can be tolerated, while providing high levels of performance.