- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Recently Accepted Articles ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Volume 2008 (2008), Article ID 218565, 8 pages
Delay Efficient 32-Bit Carry-Skip Adder
Department of Electrical and Computer Engineering, State University of New York, 1 Hawk Dr, New Paltz, NY 12561-2443, USA
Received 27 April 2007; Accepted 9 December 2007
Academic Editor: Jean-Baptiste Begueret
Copyright © 2008 Yu Shen Lin and Damu Radhakrishnan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- I. Koren, Computer Arithmetic Algorithms, A. K. Peters, Natick, Mass, USA, 2nd edition, 2002.
- B. Parhami, Computer Arithmetic Algorithms and Hardware Designs, Oxford University Press, Oxford, UK, 2000.
- C. Nagendra, M. J. Irwin, and R. M. Owens, “Area-time-power tradeoffs in parallel adders,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 10, pp. 689–702, 1996.
- K. Chirca, M. Schulte, J. Glossner, et al., “A static low-power, high-performance 32-bit carry skip adder,” in Proceedings of the EUROMICRO Symposium on Digital System Design (DSD '04), pp. 615–619, Rennes, France, August-September 2004.
- R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Transactions on Computers, vol. 31, no. 3, pp. 260–264, 1982.
- B. W. Y. Wei, C. D. Thompson, and Y. F. Chen, “Time optimal design of a CMOS adder,” in Proceedings of the 19th Annual Asilomar Conference on Circuits, Systems, and Computers, pp. 186–191, Pacific Grove, CA, USA, November 1985.
- T. P. Kelliher, R. M. Owens, M. J. Irwin, and T.-T. Hwang, “ELM-A fast addition algorithm discovered by a program,” IEEE Transactions on Computers, vol. 41, no. 9, pp. 1181–1184, 1992.
- V. Kantabutra, “Designing optimum one-level carry-skip adders,” IEEE Transactions on Computers, vol. 42, no. 6, pp. 759–764, 1993.
- V. Kantabutra, “Accelerated two-level carry-skip adders-a type of very fast adders,” IEEE Transactions on Computers, vol. 42, no. 11, pp. 1389–1393, 1993.
- S. Goel, S. Gollamudi, A. Kumar, and M. Bayoumi, “On the design of low-energy hybrid CMOS 1-bit full adder cells,” in Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '04), vol. 2, pp. 209–212, Hiroshima, Japan, July 2004.
- E. Gayles, R. M. Owens, and M. J. Irwin, “Low power circuit techniques for fast carry-skip adders,” in Proceedings of the 39th IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp. 87–90, Ames, Iowa, USA, August 1996.