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VLSI Design
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2008
/
Article
/
Tab 2
/
Research Article
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver
Table 2
Fixed-point quantization rules.
Signal
Q1
Q2
Q3
Range
Bits
Range
Bits
Range
Bits
Inputs
(
−
8
.
0
,
8
.
0
)
,
1
1
(
−
8
.
0
,
8
.
0
)
1
0
ℎ
𝑟
𝑖
,
𝑗
ℎ
𝑖
𝑖
,
𝑗
(
−
8
.
0
,
8
.
0
)
1
2
(
−
4
.
0
,
4
.
0
)
,
1
0
(
−
4
.
0
,
4
.
0
)
9
…
(
−
1
6
.
0
,
1
6
.
0
)
(
−
1
6
.
0
,
1
6
.
0
)
1
4
Output of
(
−
1
6
.
0
,
1
6
.
0
)
(combined signal path)
M1
1
3
14
(
−
1
6
.
0
,
1
6
.
0
)
1
5
(
−
1
6
.
0
,
1
6
.
0
)
1
3
A1
(
−
1
6
.
0
,
1
6
.
0
)
1
2
(
−
3
2
.
0
,
3
2
.
0
)
1
6
(
−
3
2
.
0
,
3
2
.
0
)
1
3
A2
(
−
3
2
.
0
,
3
2
.
0
)
1
2
…
(
0
.
0
,
1
6
.
0
)
1
4
(
0
.
0
,
1
6
.
0
)
Output of
1
2
(equivalent channel path)
M1
(
0
.
0
,
1
6
.
0
)
1
1
(
0
.
0
,
1
6
.
0
)
1
5
(
0
.
0
,
1
6
.
0
)
1
1
A1
(
0
.
0
,
1
6
.
0
)
1
0
(
0
.
0
,
3
2
.
0
)
1
6
(
0
.
0
,
1
6
.
0
)
1
0
A2
(
0
.
0
,
1
6
.
0
)
9
𝑥
𝑟
𝑥
𝑖
(
−
3
2
.
0
,
3
2
.
0
)
1
4
Global outputs
(
−
3
2
.
0
,
3
2
.
0
)
,
1
2
(
−
3
2
.
0
,
3
2
.
0
)
1
1
ℋ
(
0
.
0
,
3
2
.
0
)
1
4
(
0
.
0
,
3
2
.
0
)
1
0
(
0
.
0
,
3
2
.
0
)
𝑁
𝑢
=
1
5
5
d
B
4
5
d
B
3
5
d
B
9
