VLSI Design

Research Article

Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

Table 3

Synthesis results for the MIMO decoding module.
DSP48Flip-flopsSlicesLUTsLogicRoute-throughShift registersDSP slicesMin. clock cycle (ns)
Q1Auto 5 5 6 2 8 2 4 7 . 9 6 5 6 5 1 3 4 0 5 6 3 2 1 1 0 5
Q1Yes 0 6 2 1 6 4 9 9 . 5 5 4 4 1 9 2 4 3 5 4 5 4 4 9 2
Q2Yes 0 4 4 5 2 4 9 9 . 9 8 5 4 2 3 2 4 9 5 4 9 4 6 4 8 9
Q2Auto 5 4 4 5 2 2 4 6 . 5 7 7 7 5 9 3 9 6 3 7 6 2 8 3 1 6 3
Q2No 1 3 4 4 5 2 0 5 . 5 2 4 3 9 0 2 3 0 8 4 5 1 5 4 3 6
Q3Auto 5 4 0 7 4 2 4 6 . 9 5 6 1 0 0 M H z