Enabling VLSI Processing Blocks for MIMO-OFDM Communications

Table 4

FPGA synthesis results for matrix factorization building block.

Tech. μm	xc4vlx200	xc2v1000	xc4vlx200
Handled matrices	8×8 Real	4×4 Complex	4×4 Complex
Array	TA	LA	SE
no. of PEs	32	4	2
fclk MHz	89	101	115
Area	8321(9%)	1666 Slices (32%)	9117 Slices (10%) +
	92 DSP48	4 BRAM (10%)	22 DSP48 (23%) + 9 BRAM (3%)
Throughput	1.85 Mmat/s	0.45 Mmat/s	0.15 Mmat/s