]>A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators : Figure 10
512946.fig.010a
(a)
512946.fig.010b
(b)
Figure 10: The measurement jitter histogram of the proposed PLL with the 250 mVrms supply noise. (a) The supply noise is provided to the dual regulators. (b) The supply noise is coupled directly to the CP and the VCO.