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Volume 2008 (2008), Article ID 674259, 7 pages
Power Considerations in Banked CAMs: A Leakage Reduction Approach
Departamento de Ingeniería Electrónica, Universidad Politécnica de Madrid, 28040 Madrid, Spain
Received 26 April 2007; Accepted 9 December 2007
Academic Editor: Jean-Baptiste Begueret
Copyright © 2008 Pedro Echeverría et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- S. Swaminathan, S. B. Patel, J. Dieffenderfer, and J. Silberman, “Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor,” in Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED '05), pp. 54–58, San Jose, Calif, USA, March 2005.
- K.-J. Lin and C.-W. Wu, “A low-power CAM design for LZ data compression,” IEEE Transactions on Computers, vol. 49, no. 10, pp. 1139–1145, 2000.
- Y. Tang, Y. Jiang, and Y. Wang, “CAM-based label search engine for MPLS over ATM networks,” in Proceedings of IEEE Global Telecommunications Conference (GLOBECOM '01), vol. 1, pp. 45–49, San Antonio, Tex, USA, November 2001.
- H. Liu, “Reducing routing table size using ternary-CAM,” in Proceedings of the 9th Symposium on High Performance Interconnects (HOTI '01), pp. 69–73, Stanford, Calif, USA, August 2001.
- I. Arsovski and A. Sheikholeslami, “A current-saving match-line sensing scheme for content-addressable memories,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '03), vol. 1, pp. 304–494, San Francisco, Calif, USA, February 2003.
- H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed lowpower CMOS fully parallel content-addressable memory macros,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 956–968, 2001.
- I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1958–1966, 2003.
- K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '03), pp. 383–386, San Jose, Calif, USA, September 2003.
- S. Choi, K. Sohn, and H.-J. Yoo, “A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 254–260, 2005.
- C.-S. Lin, J.-C. Chang, and B.-D. Liu, “A low-power precomputation-based fully paralel content-addressable memory,” IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 654–662, 2003.
- H. Noda, K. Inoue, M. Kuroiwa, et al., “A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 245–253, 2005.
- N. S. Kim, T. Austin, D. Blaauw, et al., “Leakage current: Moore's law meets static power,” Computer, vol. 36, no. 12, pp. 68–75, 2003.
- P. Echeverría, J. L. Ayala, and M. López-Vallejo, “A banked precomputation-based CAM architecture for low-power storage-demanding Applications,” in Proceedings of the 13th IEEE Mediterranean Electrotechnical Conference (MELECON '06), pp. 57–60, Malaga, Spain, May 2006.
- P. Echeverría, J. L. Ayala, and M. López-Vallejo, “Leakage energy reduction in banked content addressable memories,” in Proceedings of the 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS '06), pp. 1196–1199, Nice, France, December 2006.
- K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. N. Mudge, “Drowsy caches: simple techniques for reducing leakage power,” in Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA '02), pp. 148–157, Anchorage, Alaska, USA, May 2002.
- N. S. Kim, K. Flautner, D. Blaauw, and T. N. Mudge, “Single-VDD and single-VT super-drowsy techniques for low-leakage high-performance instruction caches,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '04), pp. 54–57, Newport, Calif, USA, August 2004.