VLSI Design

Research Article

Wave Pipelining Using Self Reset Logic

Figure 8

Advancing waves: 𝑐 𝑙 𝑘 , output: 𝑞 𝑟 𝑙 ⟨ 1 5 ∶ 0 ⟩ , and inputs 𝑑 𝑎 𝑝 and 𝑑 𝑏 𝑝 .
738983.fig.008