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Volume 2008 (2008), Article ID 738983, 6 pages
Wave Pipelining Using Self Reset Logic
Department of Electrical Engineering, School of Engineering, Santa Clara University, 500 El Camino Real, Santa Clara, CA 95053, USA
Received 1 May 2007; Accepted 9 December 2007
Academic Editor: Jean-Baptiste Begueret
Copyright © 2008 Miguel E. Litvin and Samiha Mourad. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- M. E. Litvin, Wave pipelining with self reset logic, Doctoral dissertation.
- M. E. Litvin and S. Mourad, “Self reset logic for fast arithmetic applications,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 4, pp. 462–475, 2005.
- M. E. Litvin and S. Mourad, “Wave pipelining with self reset logic,” in Proceedings of IEEE International Conference on Electronic Circuits & Systems (ICECS '06), Nice, France, December 2006.
- E. F. Klass, Wave pipelining theoretical & practical issues in CMOS, Doctoral dissertation.
- W. K. C. Lam, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Valid clocking in wavepipelined circuits,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '92), pp. 518–525, Santa Clara, Calif, USA, November 1992.
- L. Wentai, C. T. Gray, D. Fan, W. J. Farlow, T. A. Hughes, and R. K. Cavin, “250-MHz wave pipelined adder in 2- CMOS,” IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1117–1128, 1994.