A Multilevel Congestion-Based Global Router

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="537341.fig.001a" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.001a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Three pins to be connected in a 3-dimensional routing grid</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="537341.fig.001b" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.001b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>The 2-dimensional plan view projection of the grid</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="537341.fig.001c" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.001c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>The 2-dimensional route</td></tr></table></td></tr><tr class="fig-image" id="d"><td><img alt="537341.fig.001d" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.001d.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(d) </b>The route after layer assignment</td></tr></table></td></tr></table>

<table>An example of converting a placement into a routing grid graph [<a href="/journals/vlsi/2009/537341/#B17">17</a>].</table>

VLSI Design

A Multilevel Congestion-Based Global Router

Figure 1