VLSI Design
Volume 2009 (2009), Article ID 749272, 10 pages
doi:10.1155/2009/749272
Research Article

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

Peter Nilsson

Department of Electrical and Information Technology, Faculty of Engineering, Lund University, Box 118, 22100 Lund, Sweden

Received 9 July 2009; Revised 23 September 2009; Accepted 9 October 2009

Academic Editor: Israel Koren

Copyright © 2009 Peter Nilsson. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Peter Nilsson, “Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS,” VLSI Design, vol. 2009, Article ID 749272, 10 pages, 2009. doi:10.1155/2009/749272