Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS : Figure 1

]>Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS : Figure 1

(a)

(b)

(c)

Figure 1: A bit-parallel ripple-carry adder in (a), a bit-serial adder in (b), and a 4-bit digit-serial adder in (c).