A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor : Table 3

]>A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor : Table 3

Table 3: The comparison between proposed XORs.


	Input voltages and margins	Output margine	Number of components	Performance	Design consideration

6-transistor XOR	High Logic: 5 V	Not mentioned	FET : 6	Simulation results up to 50 MHz, Maximum delay:	There are two types of implementation with different characteristics
	Low Logic: 0 V			Figure 3(a): 3.98 nanoseconds
				Figure 3(b): 1.75 nanoseconds

4-transistor XOR	High Logic: 3.3 V	Not mentioned	FET : 4	Simulation results up to 200 MHz, delay: 350 picoseconds	No power supply (powerless design)
	Low Logic: 0 V

Quenching of series-connected NDR devices	High Logic: 0.5 V	Not mentioned	RTD : 3	Not mentioned	For the XOR function, two FETs can be eliminated by exact design of each RTD area
	Low Logic: 0 V		FET : 6

RTHEMT XOR (This paper)	High Logic: 1.1–1.4 V	High logic:	FET: 2	Max Freq: 90.90 GHz	1. One state has nearly zero static power dissipation.
	Low Logic: 0–0.3 V	Low Logic:	RTHEMT: 1	Max Delay: 11 picoseconds	2. In highest frequency it dissipates only