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Special Issues
VLSI Design
/
2009
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Article
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Tab 1
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Research Article
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
Table 1
Synthesis results of the routers on a Virtex2 FPGA device (flit size:
bits, FIFO buffer depth: 8).
Routing Al.
XY
WF
EL
OE
NF
Number of slices
4884
5009
5016
5017
5114
Max. freq. (MHz)
83.39
91.02
89.43
88.57
100.51