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VLSI Design
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Special Issues
VLSI Design
/
2009
/
Article
/
Tab 4
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Research Article
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
Table 4
Logic synthesis of the router prototype with static XY routing algorithm (flit size: 32 + 6 bits) using UMC 130-nm and 180-nm standard-cell technologies.
130-nm techn.
FIFO depth: 2
FIFO depth: 4
Num. of logic cells
5363
6661
Total cell area (
)
0.0767
0.1018
Max. Freq. (MHz)
472
453
180-nm techn.
FIFO depth: 2
FIFO depth: 4
Num. of logic cells
5033
6572
Total cell area (
)
0.123
0.168
Max. freq. (MHz)
264
247