Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2010
/
Article
/
Fig 5
/
Research Article
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
Figure 5
Delay Distribution of 2-b WBTC before Optimization.