Research Article

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Table 1

Timing Paths in 2-b WBTC.

Path No.TransistorsPath No.Transistors

1T28, T0, T4, T11, T22, T2618T28, T7, T8, T12, T18
2T28, T7, T11, T22, T2619T28, T7, T11, T15, T18
3T28, T19, T22, T2620T28, T7, T11, T17, T21
4T28, T24, T2621T28, T7, T11, T20, T21
5T28, T0, T4, T11, T17, T2322T28, T14, T15, T18
6T28, T0, T4, T11, T20, T2323T28, T14, T17, T21
7T28, T0, T4, T11, T22, T2524T28, T19, T20, T21
8T28, T7, T11, T17, T2325T28, T0, T1, T5, T13
9T28, T7, T11, T20, T2326T28, T0, T4, T11, T15, T16
10T28, T7, T11, T22, T2527T28, T7, T8, T9, T13
11T28, T14, T17, T2328T28, T7, T8, T12, T16
12T28, T19, T20, T2329T28, T7, T11, T15, T16
13T28, T19, T22, T2530T28, T14, T15, T16
14T28, T24, T2531T28, T0, T1, T2, T6
15T28, T0, T4, T11, T15, T1832T28, T0, T1, T5, T10
16T28, T0, T4, T11, T17, T2133T28, T7, T8, T9, T10
17T28, T0, T4, T11, T20, T2134T28, T0, T1, T2, T3