Research Article
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
Table 6
POINT Optimization Flow results.
| Design | # Inputs | # Outputs | # Gates | Delay reduction (%) | Uncertainty reduction (%) |
| 74181 | 14 | 8 | 74 | 43 | 14 | c2670 | 233 | 140 | 1193 | 39 | 32 | adder64 | 130 | 65 | 1491 | 61 | 63 | c3540 | 50 | 22 | 1669 | 32 | 40 | c5315 | 178 | 123 | 2406 | 29 | 32 | c7552 | 207 | 108 | 3512 | 26 | 31 |
| Average (%) | 38 | 35 |
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