Research Article
Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments
Table 3
Device utilization summary on Xilinx Virtex-II pro FPGA (XC2VP70).
| Network size | Number of slice registers | Number of block RAMs | Number of MULT | Used | Utilization | Used | Utilization | Used | Utilization |
| | 2497 | 7% | 8 | 2% | 12 | 3% | | 4929 | 14% | 16 | 4% | 24 | 7% | | 7390 | 22% | 24 | 7% | 36 | 10% | | 9915 | 29% | 32 | 9% | 48 | 14% | | 12403 | 37% | 40 | 12% | 60 | 18% | | 3661 | 11% | 8 | 2% | 18 | 5% | | 7327 | 22% | 16 | 4% | 36 | 10% | | 11025 | 33% | 24 | 7% | 54 | 16% | | 14788 | 44% | 32 | 39% | 72 | 9% | | 18461 | 55% | 40 | 12% | 90 | 27% | | 22233 | 67% | 48 | 14% | 108 | 33% | | 25652 | 77% | 56 | 17% | 126 | 38% | | 29254 | 88% | 64 | 19% | 144 | 43% | | 4783 | 14% | 8 | 2% | 24 | 7% | | 9646 | 29% | 16 | 4% | 48 | 14% | | 14561 | 44% | 24 | 7% | 72 | 21% | | 19534 | 59% | 32 | 9% | 96 | 29% | | 24470 | 73% | 40 | 12% | 120 | 36% | | 29221 | 88% | 48 | 14% | 144 | 43% | | 34389 | 103% | 56 | 17% | 168 | 51% |
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