Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Table 10

Comparison of timing complexity and target parameter in optimization between transistor sizing algorithms.

Algorithm	Initial time	Time complexity	Target parameter
MDE	—	$O(N·K^2·{|\text{FO}|}^2)$	Delay
		$N$: Number of gates, $K$: Number of different sizes of a gate $|\text{FO}|$: Maximum fan-out of a gate
ADC	—	$O(n)$	Area-Delay Product
		$N$: Number of transistors
Chang’s Algorithm	—	$O(mn)$	Any of circuit specifications including power consumption, delay, power-delay product, chip area, or their combination
		$m$: Number of steps, $n$: Number of transistors' groups
SEA	$T_{\mathrm{int}\hspace{0.17em}}=(n+1)t_{\text{swp}}<\epsilon$	$O(mn)$
	$n$: Number of transistors, $t_{\text{swp}:}$: the time needed for a sweep	$m$: Number of steps, $n$: Number of transistors' groups