]>

Table 9: PDP comparison between proposed transistor sizing algorithm (SEA) and Chang’s algorithm of full adders with a supply voltage of 1.2 V.

Full Adder Algorithm Chang’s algorithm SEA Comparison C-CMOS 0.43 0.40 7.50% Improvement CPL 0.66 0.46 30.30% Improvement TFA 0.52 0.24 53.85% Improvement TGA 0.46 0.29 36.96% Improvement New 14T 0.29 0.28 3.45% Improvement 10T 2.05 1.01 50.73% Improvement New HPSC 0.30 0.31 3.33% Degradation Average Improvement: 25.64%