Error Immune Logic for Low-Power Probabilistic Computing

Figure 3

(a) Amplified thermal noise measured from a 0.35 $\mu m$ chip. (b) Plot showing the derivation of probability of a digital “1” or “0” when thermal noise and a probability select signal are both put through a comparator. Data was collected to verify probability of error when CMOS logic is subject to noise.

(a)

(b)