Error Immune Logic for Low-Power Probabilistic Computing
Figure 5
This circuit illustrates the definitions for and . Symbol is the error probability for a node and is the probability that a network of gates is erroneous. For a single gate, is the error probability of that gate inclusive of the fact that the inputs may be erroneous. Each gate is represented by a matrix and the matrices from each level of the circuit are multiplied to get the final PTM.