Error Immune Logic for Low-Power Probabilistic Computing

<table><math id="M92" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><mi>δ</mi></mrow></math> versus <math id="M93" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><mi>ϵ</mi></mrow></math> for a NAND2 gate and an XOR2 gate.</table>

VLSI Design

fig6

Figure 6

Figure 6: Error Immune Logic for Low-Power Probabilistic Computing 