Error Immune Logic for Low-Power Probabilistic Computing

<table><math id="M108" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><mi>δ</mi></mrow></math> versus Logic Depth for an inverter chain for <math id="M109" xmlns="http://www.w3.org/1998/Math/MathML"><mi>ϵ</mi><mo>=</mo><mrow><mo stretchy="false">{</mo><mrow><mn>0.01,0.05,0.1</mn></mrow><mo stretchy="false">}</mo></mrow></math>.</table>

VLSI Design

fig7

Figure 7

Figure 7: Error Immune Logic for Low-Power Probabilistic Computing 