Error Immune Logic for Low-Power Probabilistic Computing

Table 1

$\delta$ for 2 and 3-input Gates for $ϵ=.005$.

Gate	$\delta$	Gate	$\delta$
NAND2	.0099	XOR2	.0149
NAND3	.0087	XOR3	.0197
AOI3	.0112	MIN3	.0124
NOR2	.0099	NOR3	.0087