Error Immune Logic for Low-Power Probabilistic Computing

Table 4

simulation results for 4 different full-adder implementations in TSMC $0.25\hspace{0.17em}\mu m$ at $ϵ=.005$ ($V_{\text{dd}}=1.2\hspace{0.17em}V\text{,}$$U_n=0.3\hspace{0.17em}V$).

FA Type	Energy (pJ)	$C_{\text{out}}$ delay (ns)	$C_{\text{out}}\hspace{0.17em}\hspace{0.17em}\delta$	Energy savings versus deterministic
async	0.691	1.07	.0159	$\mathrm{\hspace{0.17em}\hspace{0.17em}}5.91X$
f28	1.409	1.96	.0173	$\mathrm{\hspace{0.17em}\hspace{0.17em}}2.90X$
fmaj	1.549	2.22	.0196	$\mathrm{\hspace{0.17em}\hspace{0.17em}}2.64X$
fbase	4.087	1.19	—	—