Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

<table>Simulated SNDR versus power consumption from the reference ladder for series-split (SSC) and binary-weighted split-capacitor array (BWSC).</table>

VLSI Design

fig11

Figure 11

Figure 11: Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs 