Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

<table>Behavioral simulation of 1000 Monte Carlo SNDR versus the percentage of the top-plate parasitic capacitance <math id="M126" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><mi>β</mi></mrow></math> of series-split capacitor array at 6- to 12-bit level.</table>

VLSI Design

fig6

Figure 6

Figure 6: Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs 