Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Table 1

Performance Summary of the SAR ADC.

Technology	90-nm CMOS with MIM
Resolution	8 bit
Sampling Rate	180 MS/s
Supply Voltage	1.2 V
Full Scale Analog Input	1.2 Vpp differential
SNDR (@$f_{\text{in}}=76\hspace{0.17em}\text{MHz}$)	48 dB
SFDR (@$f_{\text{in}}=76\hspace{0.17em}\text{MHz}$)	58 dB
ENOB (@$f_{\text{in}}=76\hspace{0.17em}\text{MHz}$)	7.7 bit
FOM	0.37 pJ/conversion step
DNL	$\pm$0.5 LSB
INL	$\pm$0.5 LSB
Power Consumption
Analog	9.4 mW
Digital	2.3 mW
Reference ladder	2.3 mW
Total	14 mW