About this Journal Submit a Manuscript Table of Contents
VLSI Design
Volume 2010 (2010), Article ID 794891, 19 pages
http://dx.doi.org/10.1155/2010/794891
Review Article

CORDIC Architectures: A Survey

Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, West Bengal 721302, India

Received 6 October 2009; Accepted 10 January 2010

Academic Editor: Kiyoung Choi

Copyright © 2010 B. Lakshmi and A. S. Dhar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. D. S. Cochran, “Algorithms and accuracy in the HP-35,” Hewlett-Packard Journal, vol. 23, no. 10, 1972.
  2. J.-M. Muller, Elementary Functions: Algorithms and Implementation, Birkhäuser, Boston, Mass, USA, 2004.
  3. J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Transactions on Electronic Computers, vol. 8, no. 3, pp. 330–334, 1959.
  4. J. E. Volder, “The birth of CORDIC,” Journal of VLSI Signal Processing, vol. 25, no. 2, pp. 101–105, 2000. View at Publisher · View at Google Scholar · View at Scopus
  5. D. H. Daggett, “Decimal-binary conversions in CORDIC,” IRE Transactions on Electronic Computers, vol. 8, pp. 335–339, 1959.
  6. J. E. Meggitt, “Pseudo division and pseudo multiplication processes,” IBM Journal, vol. 6, no. 2, pp. 210–226, 1962.
  7. J. S. Walther, “A unified algorithm for elementary functions,” in Proceedings of the AFIPS Spring Joint Computer Conference, pp. 379–385, May 1971.
  8. J. S. Walther, “The story of Unified CORDIC,” Journal of VLSI Signal Processing, vol. 25, no. 2, pp. 107–112, 2000. View at Publisher · View at Google Scholar · View at Scopus
  9. G. L. Haviland and A. A. Tuszynski, “A CORDIC arithmetic processor chip,” IEEE Journal of Solid-State Circuits, vol. 15, no. 1, pp. 4–15, 1980. View at Scopus
  10. Y. H. Hu, “CORDIC-based VLSI architectures for digital signal processing,” IEEE Signal Processing Magazine, vol. 9, no. 3, pp. 16–35, 1992. View at Publisher · View at Google Scholar · View at Scopus
  11. A. A. J. de Lange, A. J. van der Hoeven, E. F. Deprettere, and J. Bu, “Optimal floating-point pipeline CMOS CORDIC processor,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '88), vol. 3, pp. 2043–2047, June 1988.
  12. A. A. J. de Lange, A. J. van der Hoeven, E. F. Deprettere, and P. Dewilde, “An application specific IC for digital signal processing: the floating point pipeline CORDIC processor,” in Proceedings of the European Conference on ASIC Design (ASIC '90), pp. 62–67, May 1990.
  13. D. E. Metafas and C. E. Goutis, “A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms,” Microprocessing and Microprogramming, vol. 30, no. 1–5, pp. 51–57, 1990. View at Scopus
  14. D. Timmermann, H. Hahn, B. J. Hosticka, and G. Schmidt, “A programmable CORDIC chip for digital signal processing applications,” IEEE Journal of Solid-State Circuits, vol. 26, no. 9, pp. 1317–1321, 1991. View at Publisher · View at Google Scholar · View at Scopus
  15. A. A. J. de Lange and E. F. Deprettere, “Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing,” in Proceedings of the 10th IEEE Symposium on Computer Arithmetic, pp. 272–281, June 1991.
  16. A. M. Despain, “Fourier transform computers using CORDIC iterations,” IEEE Transactions on Computers, vol. 23, no. 10, pp. 993–1001, 1974. View at Scopus
  17. H. M. Ahmed, J.-M. Delosme, and M. Morf, “Highly concurrent computing structures for matrix arithmetic and signal processing,” Computer, vol. 15, no. 1, pp. 65–82, 1982. View at Scopus
  18. Y. H. Hu and S. Naganathan, “A novel implementation of a chirp Z-transform using a CORDIC processor,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 38, no. 2, pp. 352–354, 1990. View at Publisher · View at Google Scholar · View at Scopus
  19. A. S. Dhar and S. Banerjee, “An array architecture for fast computation of discrete Hartley transform,” IEEE transactions on circuits and systems, vol. 38, no. 9, pp. 1095–1098, 1991. View at Publisher · View at Google Scholar · View at Scopus
  20. K. Maharatna, A. S. Dhar, and S. Banerjee, “A VLSI array architecture for realization of DFT, DHT, DCT and DST,” Signal Processing, vol. 81, no. 9, pp. 1813–1822, 2001. View at Publisher · View at Google Scholar · View at Scopus
  21. K. C. Ray and A. S. Dhar, “CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis,” IEE Proceedings: Circuits, Devices and Systems, vol. 153, no. 6, pp. 539–544, 2006. View at Publisher · View at Google Scholar · View at Scopus
  22. S. K. Rao and T. Kailath, “Orthogonal digital filters for VLSI implementation,” IEEE transactions on circuits and systems, vol. 31, no. 11, pp. 933–945, 1984. View at Scopus
  23. P. P. Vaidyanathan, “A unified approach to orthogonal digital filters and wave digital filters based on LBR two pair extraction,” IEEE transactions on circuits and systems, vol. 32, no. 7, pp. 673–686, 1985. View at Scopus
  24. Y. H. Hu and H. E. Liao, “CALF: a CORDIC adaptive lattice filter,” IEEE Transactions on Signal Processing, vol. 40, no. 4, pp. 990–993, 1992. View at Publisher · View at Google Scholar · View at Scopus
  25. J. R. Cavallaro and F. T. Luk, “CORDIC arithmetic for an SVD processor,” Journal of Parallel and Distributed Computing, vol. 5, no. 3, pp. 271–290, 1988. View at Scopus
  26. J. A. Lee and T. Lang, “SVD by constant-factor-redundant-CORDIC,” in Proceedings of the 10th IEEE Symposium on Computer Arithmetic, pp. 264–271, June 1991.
  27. A. Banerjee, A. S. Dhar, and S. Banerjee, “FPGA realization of a CORDIC based FFT processor for biomedical signal processing,” Microprocessors and Microsystems, vol. 25, no. 3, pp. 131–142, 2001. View at Publisher · View at Google Scholar · View at Scopus
  28. A. Meyer-Bäse, R. Watzel, U. Meyer-Bäse, and S. Foo, “A parallel CORDIC architecture dedicated to compute the Gaussian potential function in neural networks,” Engineering Applications of Artificial Intelligence, vol. 16, no. 7-8, pp. 595–605, 2003. View at Publisher · View at Google Scholar · View at Scopus
  29. C. Y. Kang and E. E. Swartzlander Jr., “Digit-pipelined direct digital frequency synthesis based on differential CORDIC,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 5, pp. 1035–1044, 2006. View at Publisher · View at Google Scholar · View at Scopus
  30. H. Wang, P. Leray, and J. Palicot, “Reconfigurable architecture for MIMO systems based on CORDIC operators,” Comptes Rendus Physique, vol. 7, no. 7, pp. 735–750, 2006. View at Publisher · View at Google Scholar · View at Scopus
  31. G. J. Hekstra and E. F. A. Deprettere, “Fast rotations: low-cost arithmetic methods for orthonormal rotation,” in Proceedings of the 13th IEEE Symposium on Computer Arithmetic, pp. 116–125, October 1997.
  32. K. Hwang, Computer Arithmetic: Principles, Architecture and Design, John Wiley & Sons, New York, NY, USA, 1979.
  33. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, New York, NY, USA, 1999.
  34. A. Avizienis, “Signed-digit number representation for fast parallel arithmetic,” IRE Transactions on Electronic Computers, vol. 10, pp. 389–400, 1961.
  35. D. E. Atkins, “Introduction to the role of redundancy in computer arithmetic,” IEEE Computer Magazine, vol. 8, no. 6, pp. 74–77, 1975.
  36. B. Parhami, “Carry-free addition of recorded binary signed-digit numbers,” IEEE Transactions on Computers, vol. 37, no. 11, pp. 1470–1476, 1988. View at Publisher · View at Google Scholar · View at Scopus
  37. B. Parhami, “Generalized signed-digit number systems: a unifying framework for redundant number representations,” IEEE Transactions on Computers, vol. 39, no. 1, pp. 89–98, 1990. View at Publisher · View at Google Scholar · View at Scopus
  38. T. G. Noll, “Carry-save arithmetic for high-speed digital signal processing,” in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 982–986, May 1990.
  39. R. Andraka, “A survey of CORDIC algorithms for FPGA based computers,” in Proceedings of the 6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '98), pp. 191–200, February 1998.
  40. P. W. Baker, “Suggestion for a fast binary sine/cosine generator,” IEEE Transactions on Computers, vol. 25, no. 11, pp. 1134–1136, 1976. View at Scopus
  41. Y. H. Hu, “Pipelined CORDIC architecture for the implementation of rotational based algorithm,” in Proceedings of the International Symposium on VLSI Technology, Systems and Applications, p. 259, May 1985.
  42. M. D. Ercegovac and T. Lang, “Fast cosine/sine implementation using on-line CORIC,” in Proceedings of the 21st Asilomar Conference on Signals, Systems, and Computers, 1987.
  43. E. Antelo, J. Villalba, J. D. Bruguera, and E. L. Zapata, “High performance rotation architectures based on the Radix-4 CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 8, pp. 855–870, 1997. View at Scopus
  44. D. Timmermann, H. Hahn, B. J. Hosticka, and B. Rix, “A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms,” The VLSI Journal on Integration, vol. 11, no. 1, pp. 85–100, 1991. View at Scopus
  45. J. Villalba, J. A. Hidalgo, E. L. Zapata, E. Antelo, and J. D. Bruguera, “CORDIC architectures with parallel compensation of the scale factor,” in Proceedings of the International Conference on Application Specific Array Processors, pp. 258–269, Strasbourg, France, July 1995.
  46. X. Hu, R. G. Harber, and S. C. Bass, “Expanding the range of convergence of the CORDIC algorithm,” IEEE Transactions on Computers, vol. 40, no. 1, pp. 13–21, 1991. View at Publisher · View at Google Scholar · View at Scopus
  47. Y. H. Hu, “The quantization effects of the CORDIC algorithm,” IEEE Transactions on Signal Processing, vol. 40, no. 4, pp. 834–844, 1992. View at Publisher · View at Google Scholar · View at Scopus
  48. M. D. Erecegovac and T. Lang, Digital Arithmetic, Elsevier, Amsterdam, The Netherlands, 2004.
  49. E. Antelo, J. Villalba, and E. L. Zapata, “A low-latency pipelined 2D and 3D CORDIC processors,” IEEE Transactions on Computers, vol. 57, no. 3, pp. 404–417, 2008. View at Publisher · View at Google Scholar · View at Scopus
  50. H. M. Ahmed, “Efficient elementary function generation with multipliers,” in Proceedings of the 9th Symposium on Computer Arithmetic, pp. 52–59, September 1989.
  51. N. Takagi, T. Asada, and S. Yajima, “Redundant CORDIC methods with a constant scale factor for sine and cosine computation,” IEEE Transactions on Computers, vol. 40, no. 9, pp. 989–995, 1991.
  52. J. Duprat and J.-M. Muller, “The CORDIC algorithm: new results for fast VLSI implementation,” IEEE Transactions on Computers, vol. 42, no. 2, pp. 168–178, 1993. View at Publisher · View at Google Scholar · View at Scopus
  53. D. S. Phatak, “Double step branching CORDIC: a new algorithm for fast sine and cosine generation,” IEEE Transactions on Computers, vol. 47, no. 5, pp. 587–602, 1998. View at Scopus
  54. J. A. Lee and T. Lang, “Constant-factor redundant CORDIC for angle calculation and rotation,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1016–1025, 1992. View at Publisher · View at Google Scholar · View at Scopus
  55. D. Timmermann, H. Hahn, and B. J. Hosticka, “Low latency time CORDIC algorithms,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1010–1015, 1992. View at Publisher · View at Google Scholar · View at Scopus
  56. H. Dawid and H. Meyr, “The differential CORDIC algorithm: constant scale factor redundant implementation without correcting iterations,” IEEE Transactions on Computers, vol. 45, no. 3, pp. 307–318, 1996. View at Scopus
  57. H. Dawid and H. Meyr, “High speed bit-level pipelined architectures for redundant CORDIC implementation,” in Proceedings of the International Conference on Application, pp. 358–372, 1992.
  58. J. D. Bruguera, E. Antelo, and E. L. Zapata, “Design of a pipelined Radix 4 CORDIC processor,” Parallel Computing, vol. 19, no. 7, pp. 729–744, 1993. View at Scopus
  59. E. Antelo, J. D. Bruguera, and E. L. Zapata, “Unified mixed Radix 2–4 redundant CORDIC processor,” IEEE Transactions on Computers, vol. 45, no. 9, pp. 1068–1073, 1996. View at Scopus
  60. S. Wang, V. Piuri, and E. E. Swartzlander Jr., “Hybrid CORDIC algorithms,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1202–1207, 1997.
  61. M. Kuhlmann and K. K. Parhi, “P-CORDIC: a precomputation based rotation CORDIC algorithm,” EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 936–943, 2002. View at Publisher · View at Google Scholar
  62. M. Kuhlmann and K. K. Parhi, “A high-speed CORDIC algorithm and architecture for DSP applications,” in Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS '99), pp. 732–741, October 1999.
  63. B. Gisuthan and T. Srikanthan, “Pipelining flat CORDIC based trigonometric function generators,” Microelectronics Journal, vol. 33, no. 1-2, pp. 77–89, 2002. View at Publisher · View at Google Scholar · View at Scopus
  64. T.-B. Juang, S.-F. Hsiao, and M.-Y. Tsai, “Para-CORDIC: parallel CORDIC rotation algorithm,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 8, pp. 1515–1524, 2004. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  65. H. S. Kebbati, J. Ph. Blonde, and F. Braun, “A new semi-flat architecture for high speed and reduced area CORDIC chip,” Microelectronics Journal, vol. 37, no. 2, pp. 181–187, 2006. View at Publisher · View at Google Scholar · View at Scopus
  66. T. Srikanthan and B. Gisuthan, “A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine-cosine generators,” Microprocessors and Microsystems, vol. 26, no. 5, pp. 243–252, 2002. View at Publisher · View at Google Scholar · View at Scopus