About this Journal Submit a Manuscript Table of Contents
VLSI Design
Volume 2010 (2010), Article ID 864165, 8 pages
http://dx.doi.org/10.1155/2010/864165
Research Article

Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

1Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803-5901, USA
2Electronics Foundations Group, AFRL/VSSE, 3550 Aberdeen Avenue SE, Kirtland AFB, NM 87117, USA

Received 1 June 2009; Accepted 19 November 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 Yao Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

1. Introduction

A good amount of work on modeling carbon nanotube field-effect transistors (CNT-FETs) has been reported [14]. However, these models are numerical-based and require a mathematical/software realization. Recently, Srivastava et al. [5, 6] have obtained an analytical solution of current transport model for the CNT-FET for analysis and design of CNT-FET-based integrated circuits. Based on their work, a dynamic model [7, 8] for CNT-FETs is obtained and Verilog-AMS language [9] is used to predict static and dynamic characteristics of CNT-FETs and integrated circuits. Verilog-AMS requires less computational steps and easy to experiment with the developing model equations. In our work, we have used Verilog-AMS to describe the CNT-FET static and dynamic models and simulated CNT-FET circuits using Cadence/Spectre.

Fetter [10, 11] and Maffucci et al. [12] have investigated electron transport along the CNT and proposed a two-dimensional fluid model. In this model [1012], electron-electron correlation, which is significant in CNT, has not been considered. In a recent work, we have made modification in two-dimensional fluid model to include electron-electron repulsive interaction and built a semiclassical one-dimensional fluid model [13], which is relatively easy to solve and apply in CNT transmission line modeling. We have also proposed circuit models for single-walled carbon nanotubes (SWCNTs) bundles as interconnects based on the one-dimensional fluid model.

2. CNT-FET Model

2.1. Static Model

The structure of a CNT-FET shown in Figure 1 [2] is similar to the structure of a typical MOSFET, where an SWCNT forms the channel between two electrodes, which work as the source and drain of the transistor. The structure is built on top of an insulating layer and a substrate which works as the back gate. The top gate is metal over the thin gate oxide. Current transport equations in a CNT-FET are developed in [5, 6] which are described here as follows and include both drift current and diffusion currents:𝐼ds=𝐼drift+𝐼di𝑓=𝛽driftΨcnt,𝑠(𝐿),𝑉gs𝑓driftΨcnt,𝑠(0),𝑉gs𝑓+𝛽diΨcnt,𝑠(𝐿),𝑉gs𝑓diΨcnt,𝑠(0),𝑉gs,(1) where𝑓drift𝜓cnt,𝑠(𝑥),𝑉gs=𝑉gs+𝑉sb𝑉fb𝜓cnt,𝑠1(𝑥)2𝜓2cnt,𝑠𝑓(𝑥),di𝜓cnt,𝑠(𝑥),𝑉gs=𝑘𝑇𝑞𝜓cnt,𝑠(𝑥),𝛽=𝛾𝜇𝐶ox1𝐿2.(2)

864165.fig.001
Figure 1: Plot of the vertical cross-section of a CNT-FET [2].

In (1), various parameters are defined as follows: we have L: gate length, 𝜇: carrier mobility, k: Boltzmann constant, T: temperature,K,𝑉fb: flat-band voltage, 𝑉gs: gate-source voltage, 𝑉sb: source-substrate voltage, 𝜓cnt,𝑠: surface potential of CNT, and 𝐶ox1: gate-oxide capacitance per unit area. For a carbon nanotube of length L and radius 𝑟 in a CNT-FET, the oxide capacitance is given by [14]𝐶ox1=2𝜋𝜀ox1𝐿𝑇lnox1+𝑟+𝑇2ox1+2𝑇ox1𝑟./𝑟(3)

In (3), 𝑇ox1 is the thickness of the gate oxide and r is the radius of the CNT. Equation (1) is modified to incorporate channel length modulation through the parameter 𝜆 as in a MOSFET. In saturation region, modified equation (1) is described as follows [6]: 𝐼ds𝑓𝜓=𝛽cnt,𝑠(𝐿),𝑉gs𝜓𝑓cnt,𝑠(0),𝑉gs1+𝜆𝑉ds.(4)

2.2. Dynamic Model

The dynamic response of a CNT-FET can be modeled using Meyer capacitance model [7, 8, 15, 16] as shown in Figure 2. Recently, we have obtained capacitances: 𝐶gs,𝐶gd, and 𝐶gb based on current transport modeling of CNT-FETs described by (1), which are as follows [7, 8].

864165.fig.002
Figure 2: Meyer capacitance model for CNT-FETs.

In linear region,𝐶gb𝐶=0,gs||𝐶=𝛾𝜇𝑊||C2ox12𝛽𝛿𝐼𝑒1𝛿Δ𝑉gs𝛿𝐼𝑒1𝛿Δ(1/2)𝑉gd(1/2)𝑉gs2×𝛿𝐼𝑒1𝛿Δ(2/3)𝑉gd(1/3)𝑉gs𝛿𝐼𝑒1𝛿Δ(1/2)𝑉gd(1/2)𝑉gs2,𝐶gd||𝐶=𝛾𝜇𝑊||C2ox12𝛽𝛿𝐼𝑒1𝛿Δ𝔄𝑉gs𝛿𝐼𝑒1𝛿Δ((1/2)𝑉gd(1/2)𝑉gs)2×𝛿𝐼𝑒1𝛿Δ𝔄(1/3)𝑉gd(2/3)𝑉gs𝛿𝐼𝑒1𝛿Δ(1/2)𝑉gd(1/2)𝑉gs2,(5) where denotes 𝜙0(Δ𝐸𝐹/𝑞)+(𝐸𝑐/𝑞)(𝑘𝑇/𝑞)+𝑉fb, 𝔄 denotes 𝜙0(Δ𝐸𝑐/𝑞)+(𝐸𝑐/𝑞)(𝑘𝑇/𝑞)+𝑉fb. In saturation region,𝐶gb𝐶=0,gs=13||𝐶𝛾𝜇𝑊||𝐶2ox1𝛽,𝐶gd=0.(6)

Considering 𝐶sb and 𝐶db to be equal to one half the insulator capacitance, 𝐶ox2/2 in series with the depletion-layer capacitance, 𝐶subs/2 [17, 18], we obtain𝐶ox2=2𝜋𝜀ox2𝐿𝑇lnox1+𝑟+𝑇2ox2+2𝑇ox2𝑟,𝐶/𝑟subs=𝑁𝐴𝑞𝜀𝑠4𝐶ox2𝑉gb𝜙ms𝜓cnt+𝑁𝐴𝑞𝜀𝑠8𝐶2ox2𝑉gb+𝑁𝐴𝑞𝜀𝑠8𝐶2ox2𝜙ms8𝐶2ox2𝜓cnt4𝐶ox2𝑉gb𝜙ms𝜓cnt,(7) where 𝜀𝑠 is the permittivity of the semiconductor, 𝑊𝑠 is the depletion region width, and 𝑁𝐴 is the doping concentration.

3. SWCNT Interconnect Model

Figure 3 shows the geometry of an SWCNT interconnect. Based on two-dimensional fluid model developed by Maffucci et al. [12] we have proposed one-dimensional fluid model to describe the electron transport in metallic CNT and built a transmission line model of metallic CNT interconnects [13]. When compared with a two-dimensional fluid model, one-dimensional fluid model is accurate and takes into account electron-electron interaction. The Lüttinger Liquid Theory [19] models SWCNT as a one-dimensional conductor from quantum concept and takes into account electron-electron correlation. However, our model is simple in mathematical modeling and easier to extend in modeling of CNT bundles as interconnections. The basic equation is Euler’s equation, which is Newton’s Second Law applied in fluid dynamics and is given by [13]𝜕𝑚𝑛𝜕𝑡+𝑣𝑧𝜕𝑣𝜕𝑧𝑧=𝜕𝑝𝜕𝑧𝑒𝑛(1𝛼)𝕰z||s𝑚𝑛𝑣𝑣𝑧,(8) where 𝑛0 is the equilibrium electron density, 𝑣𝑧 is the electron mean velocity, 𝑝 is the pressure, m is the electron mass, e is the electronic charge, and 𝑧 is electric field. The second term on the right-hand side represents Lorentz force and includes electron-electron interaction through the parameter 𝛼. The last term on the right-hand side represents the effect of scattering of electrons with the positive charge background and υis the electron relaxation frequency, 𝜐=𝑣𝐹/𝑙mfp, where 𝑙mfp is the mean-free path of electron in CNT and 𝑣𝐹 is the Fermi velocity. Length of CNT is l and sgn(𝑙) is the sign function defined as follows: sgn(𝑙)=0if𝑙<𝑙mfp,1if𝑙𝑙mfp.(9) The parameter 𝛼 describes the classical electron-electron repulsive interaction given by [13] 𝕰𝛼𝑧𝑃𝕰𝑧=𝐸𝑃𝐸=𝐸𝑃𝐸𝐾+𝐸𝑃,(10) where 𝑧𝑃 is the part of the electrical field which provides potential energy to electrons in z direction. E is the total energy of electrons. 𝐸𝑃 and 𝐸𝐾 are the potential and kinetic energies of electrons, respectively.

864165.fig.003
Figure 3: Geometry of a single-walled carbon nanotube (SWCNT).

The equation relating current density, charge density, and electric field can be described as follows [13]:𝜕𝑗(𝑧,𝑡)𝜕𝑡+𝜈𝑗+𝑢2𝑒𝜕𝜎(𝑧,𝑡)=𝑒𝜕𝑧2𝑛0𝑚(1+𝛼)𝕰𝑧.(11)

We consider a metallic single-walled CNT above a perfect conducting plane and assume [12] that the propagating EM wave is in quasi-TEM mode [12]. The voltage and current intensity are then expressed as follows:𝑖(𝑧,𝑡)=𝑗𝑧𝑑𝑙2𝜋𝑟𝑗(𝑧,𝑡),𝑞(𝑧,𝑡)=𝜎𝑑𝑙2𝜋𝑟𝜎(𝑧,𝑡).(12)

Combining (12) and (11), following equation is obtained as𝕰𝑧=𝑅𝑖+𝐿𝐾𝜕𝑖+1𝜕𝑡𝐶𝑄𝜕𝑞,𝜕𝑧(13) where 𝑅𝐿𝐾sgn(𝑙)𝜈 is the resistance per unit length of CNT, 𝐿𝐾𝑚/[(1+𝛼)2𝜋𝑟𝑒2𝑛0] is the kinetic inductance per unit length, 𝐶𝑄1/𝐿𝐾𝑢2𝑒 is quantum capacitance per unit length, and𝑢𝑒=𝑣𝐹/1𝛼 is the thermodynamic speed of sound of the electron fluid under neutral environment.

The magnetic inductance and electric capacitance per unit length of a perfect conductor on a ground plane are given by [20]𝐿𝑀=𝜇2𝜋cosh1𝑟𝜇2𝜋ln,𝐶2𝑟𝐸=2𝜋𝜀cosh1(/𝑟)2𝜋𝜀,ln(/𝑟)(14) where h is the distance of CNT to the ground plane. Equation (14) is accurate enough for >2𝑟.

4. SWCNT Bundle Interconnect Model

Carbon nanotube can also be fabricated in bundles. The spacing between nanotubes in the bundle is due to the van der Waals forces between the atoms in adjacent nanotubes [21]. One of the most critical challenges in realizing high-performance SWCNT interconnect is in controlling the proportion of metallic nanotubes in a bundle. Current SWCNT fabrication techniques cannot effectively control the chirality of the nanotubes in a bundle [22, 23]. Therefore, SWCNT bundles have metallic nanotubes that are randomly distributed within the bundle. Avouris et al. [22] and Liebau et al. [23] have shown that metallic nanotubes are distributed with a probability 𝛽=1/3 in a growth process. The proportion of metallic nanotubes can, however, be potentially increased using techniques introduced in [24, 25].

Figure 4 shows the cross-section of an SWCNT bundle. Since the van der Waals force between the carbon atoms in adjacent SWCNTs is negligible compared to covalent bond between carbon atoms in an SWCNT [26], the one-dimensional fluid model can be applied to each SWCNT in the bundle with modification.

864165.fig.004
Figure 4: Cross-section of SWCNT bundle interconnect wire.

Considering one of the SWCNTs, assuming electrons in SWCNT will be only affected by the electrons in the adjacent metallic SWCNTs and semiconducting SWCNTs have no effect on the conductance of the bundle. To calculate the potential energy, we first consider the potential energy of each SWCNT and then move them to be adjacent to each other to compose for the SWCNT bundle. Average potential energy of electrons in a single SWCNT can be described by the following equation:𝐸𝑃𝑒=622𝜋𝜀01𝑑+𝛽Γ𝑖=116𝑒22𝜋𝜀01𝑑𝑏,(15) where d is diameter of CNT and 𝑑𝑏=𝛿+𝑑 is the distance of the adjacent SWCNT shown in Figure 4. δis the spacing between the SWCNTs in the bundle corresponding to the van der Waals distance between graphene layers in graphite. Γ is the average number of SWCNTs neighboring an SWCNT. The number of SWCNTs neighboring the corner SWCNT is 2, the number of SWCNTs neighboring the edge SWCNT is 4, and the number of SWCNTs neighboring the inside SWCNT is 6. Therefore, Γ=[(6𝑁𝑥𝑁𝑦4𝑁𝑥4𝑁𝑦2[𝑁𝑦/2])/(𝑁𝑥𝑁𝑦2[𝑁𝑦/2])], where square brackets are the floor functions.

The kinetic energy of the electrons is described by𝐸𝐾1=4×2𝑚𝑣2𝐹7eV.(16)

Therefore, electron-electron interaction parameter α for SWCNT bundle can be calculated using (10). Total number of metallic SWCNTs in a bundle can be described by 𝑁=𝛽(𝑁𝑥𝑁𝑦[𝑁𝑦/2]). Following the derivation of electric field and current charge relation in [13], we get the similar equation for the electric field as described below:𝕰𝑧=𝑅𝑖+𝐿𝐾𝜕𝑖+1𝜕𝑡𝐶𝑄𝜕𝑞,𝜕𝑧(17) where 𝑅𝐿𝐾sgn(𝑙)𝜈 is the resistance per unit length of an SWCNT in an SWCNT bundle.

In (17), 𝐿𝐾𝜋/4𝑒2𝑣𝐹 is the kinetic inductance per unit length of an SWCNT in a bundle and 𝐶𝑄1/𝐿𝐾𝑢2𝑒 is the quantum capacitance per unit length of an SWCNT in a bundle. 𝑢𝑒=𝑣𝐹/1𝛼 is the thermodynamic speed of sound of the electron fluid under a neutral environment.

The SWCNTs at the bottom shield the upper SWCNTs from the ground plane. Therefore, the electric capacitance 𝐶𝐸 does not exist in the upper SWCNTs. However, there exists electric capacitance per unit length 𝐶𝑏 between the neighboring metallic SWCNTs and its value is given by [20]𝐶𝑏=𝜋𝜀0𝑑ln𝑏+/𝑑𝑑𝑏/𝑑2.1(18)

Figure 5 shows the equivalent circuit of an SWCNT bundle as an interconnect wire. 𝑁𝑏=𝑁𝑥 is the number of lowest level metallic SWCNTs, which shield upper levels SWCNTs from ground plane. 𝑁𝑎=𝑁𝑁𝑏 is the number of upper levels metallic SWCNTs.

864165.fig.005
Figure 5: Equivalent circuit of SWCNT bundle interconnect.

5. Result and Discussion

In a recent work [6], we have developed analytical CNT-FET models for I-V characteristics and verified them with the experimentally measured I-V characteristics. Table 1 summarizes some of the physical and electrical parameters of CNT-FETs and comparison with equivalent MOSFET parameters. CNT-FETs are described in [2, 6] and MOSFETs in [27, 28], respectively. It is noticed from Table 1 that the CNT-FET carries a higher current density compared with the equivalent bulk silicon and SOI MOSFETs. In the following, we have used our CNT-FET models [58] in studying the performance of a ring oscillator circuit and compared it with the measured performance.

tab1
Table 1: A comparison of modeled and measured parameters of CNT-FETs and MOSFETs.

Figure 6(a) shows schematic of a five-stage ring oscillator circuit similar to one fabricated by Chen et al. [29]. Figure 6(b) shows the simulation result of the ring oscillator output waveform at 0.92 V supply voltage. Figure 6(c) shows the oscillation frequency with varying supply voltage. The modeled curve does not include the effect of channel length modulation. The experimental data are taken from the work of Chen et al. [29]. Modeled and experimental curves show that the frequency of the ring oscillator is about 70–80 MHz at 1.04 V supply voltage. The frequency is low because CNT-FETs in this ring oscillator are 600 nm long and there are parasitic capacitances associated with the metal wire in the ring oscillator. Shorter length of CNT-FETs will increase the oscillating frequency as shown in Figure 7.

fig6
Figure 6: (a) Schematic of a 5-stage ring oscillator, (b) output waveform of ring oscillator, and (c) oscillating frequency versus supply voltage 𝑉DD. Dimensions of both the n- and p-types CNT-FETs are d = 2 nm and L = 600 nm.
864165.fig.007
Figure 7: Oscillating frequency of a 5-stage ring oscillator versus length of the CNT-FETs.

SWCNT exhibits large contact resistance when used as an interconnect wire [30]. However, CNT bundle gives low contact resistance when used as the circuit interconnect wire [31, 32]. Contact resistance in a bundle, however, will depend on the number of SWCNTs being metallic. Utilizing the models of CNT interconnects, we have also studied the performance of CNT-FET circuit inverter pair with different kinds of interconnects including the copper (Cu). One of the advantages of CNT interconnect is its large mean-free path 𝑙mfp, which is on the order of several micrometers (as compared to 40 nm for Cu at room temperature). It provides low resistivity and ballistic transport in short-length interconnects [33]. In this work, first we have simulated a CNT-FET inverter pair with 0.1 𝜇m Cu and SWCNT bundle as interconnect wires using Cadence/Spectre. We have utilized the process parameters from the 2016 node, 22 nm technology [34] and assumed a 22 nm width and 44 nm height of the SWCNT bundle. The spacing between nanotubes in the bundle is due to van der Waals forces between the atoms in adjacent nanotubes, which means that the spacing between adjacent SWCNTs is 0.34 nm. If we assume diameter of an SWCNT in a bundle is to be 1 nm, then there are nearly 500 SWCNTs in the 22 nm (width) × 44 nm (height) bundle following Figure 4.

Figure 8 shows input and output waveforms of a CNT-FET inverter pair using SWCNT bundle as an interconnect wire and comparison with the ideal interconnect (RC = 0) and Cu interconnect. Input signal is a 4 GHz square wave pulse. The average delay is 6 ps, which suggests that the CNT-FET inverter pair can respond up to 100 GHz input signal. The performance of SWCNT bundle as an interconnect wire (𝛽=1) is close to Cu interconnect. It is due to contact resistance and relatively larger capacitance in an SWCNT bundle. The average delays are smaller for 𝛽=1 than those for𝛽=1/3 for SWCNT bundle interconnect. It can be explained that there are more metallic SWCNTs in a bundle when βincreases.

864165.fig.008
Figure 8: Input and output waveforms of a CNT-FET inverter pair with 0.1 𝜇m length of different interconnect wires.

Local interconnects are often used for connecting nearby gates or devices with lengths of the order of micrometers. Therefore, these have the smallest cross-section and largest resistance per unit length compared to global interconnects.

Figure 9 shows output waveforms of a CNT-FET inverter pair using 10 𝜇m SWCNT bundle interconnect and the comparison with the ideal interconnect (RC = 0) and Cu interconnect wires. Input signal is a 15 MHz square wave pulse. The performance of SWCNT bundle (𝛽=1) interconnect is better than Cu interconnect. While the delay of SWCNT bundle (𝛽=1/3) interconnect is larger than the Cu interconnect due to contact resistance and relatively larger capacitance in an SWCNT bundle, the average delays are smaller when 𝛽=1 than 𝛽=1/3 for SWCNT bundle interconnect wires. It can also be explained that there are more metallic SWCNTs in a bundle when βincreases.

864165.fig.009
Figure 9: Output waveforms of a CNT-FET inverter pair with 10𝜇m length of different interconnect wires.

Global interconnects have larger cross-section and smaller resistivity. The lengths are of the order of hundred micrometers. Figure 10 shows output waveform of a CNT-FET inverter pair with 500 𝜇m SWCNT bundle interconnect and comparison with the ideal interconnect (RC = 0) and Cu interconnect wires. Here we have utilized the process parameters from the 2016 node, 22nm technology and assumed 33 nm width and 87 nm height of an SWCNT bundle [34]. It can be shown that there are nearly 1500 SWCNTs in the 33 nm (width) × 87 nm (height) bundle following Figure 4 assuming 1 nm diameter of an SWCNT. Input signal is a 2 MHz square wave pulse. The performance of SWCNT bundle (𝛽=1) interconnect is much better than the Cu interconnect. While the delay of SWCNT bundle (𝛽=1/3) interconnect is larger than the Cu interconnect, the average delays are smaller when 𝛽=1 than 𝛽=1/3 for SWCNT bundle interconnects. This explains further that there are more metallic SWCNTs in a bundle when βincreases.

864165.fig.0010
Figure 10: Output waveforms of a CNT-FET inverter pair with 500 𝜇m length of different interconnect wires.

Our results show that the CNT-FET circuits can potentially operate up to 100 GHz. SWCNT bundle interconnect (𝛽=1) has better performance than the Cu interconnect contrary to bundle with 𝛽=1/3. This result also compares well with the work of Nieuwoudt and Massoud [35] showing that the SWCNT bundle interconnects have larger delay than Cu interconnects for 𝛽=1/3. The proportion of metallic nanotubes can be potentially increased using techniques introduced in [24, 25]; the delay of SWCNT bundle interconnect can be smaller than that of Cu interconnect when 𝛽 approaches 1. The SWCNT bundle interconnect can potentially replace Cu interconnect in future CNT-FET circuits.

6. Conclusion

In this paper, static and dynamic models of CNT-FETs are introduced and models for SWCNT bundle interconnects are presented based on one-dimensional fluid model of SWCNTs. These models have been used to study the behavior of CNT-FET circuits such as ring oscillator and inverter pair and compared with the corresponding experimental behavior. The applicability of SWCNT bundle as interconnect wires in future design of integrated circuits has been explored theoretically and compared with the Cu interconnect wires for 22 nm technology node. Simulation results suggest that SWCNT bundle interconnect (𝛽=1) can replace Cu interconnects as the technology scales down.

Acknowledgments

Authors acknowledge the support provided by the Louisiana Economic Development Assistantship (EDA) program to carry out the proposed research. Part of the work is also supported by NSF (2009)-PFUND-138 and United States Air Force Contract no. FA9401-08-P-0129. Part of this material is also based on research sponsored by Air Force Research Laboratory under agreement number FA9453-10-1-0002. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon.

References

  1. F. Nihey, H. Kongo, Y. Ochiai, M. Yudasaka, and S. Iijima, “Carbon-nanotube field-effect transistors with very high intrinsic transconductance,” Japanese Journal of Applied Physics, vol. 42, no. 10B, pp. L1288–L1291, 2003. View at Publisher · View at Google Scholar · View at Scopus
  2. S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes,” Applied Physics Letters, vol. 80, no. 20, pp. 3817–3819, 2002. View at Publisher · View at Google Scholar · View at Scopus
  3. J. W. Park, J. B. Choi, and K.-H. Yoo, “Formation of a quantum dot in a single-walled carbon nanotube using the Al top-gates,” Applied Physics Letters, vol. 81, no. 14, pp. 2644–2646, 2002. View at Publisher · View at Google Scholar · View at Scopus
  4. F. Nihey, H. Hongo, M. Yudasaka, and S. Iijima, “A top-gate carbon-nanotube field-effect transistor with a titanium-dioxide insulator,” Japanese Journal of Applied Physics, vol. 41, no. 10A, pp. L1049–L1051, 2002. View at Scopus
  5. J. M. Marulanda, A. Srivastava, and A. K. Sharma, “Current transport modeling in carbon nanotube field effect transistors (CNT-FETs) and bio-sensing applications,” in Nanosensors and Microsensors for Bio-Systems, vol. 6931 of Proceedings of SPIE, San Diego, Calif, USA, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  6. A. Srivastava, J. M. Marulanda, Y. Xu, and A. K. Sharma, “Current transport modeling of carbon nanotube field effect transistors,” Physica Status Solidi A, vol. 206, no. 7, pp. 1569–1578, 2009. View at Publisher · View at Google Scholar · View at Scopus
  7. Y. Xu and A. Srivastava, “Transient behavior of integrated carbon nanotube field effect transistor circuits and bio-sensing applications,” in Nano-, Bio, and Info-Tech Sensors and Systems, vol. 7291 of Proceedings of SPIE, San Diego, Calif, USA, March 2009. View at Publisher · View at Google Scholar · View at Scopus
  8. Y. Xu and A. Srivastava, “Dynamic response of carbon nanotube field effect transistor circuits,” in Proceedings of the NSTI Nanotechnology Conference and Expo, vol. 1, pp. 625–628, Houston, Tex, USA, May 2009. View at Scopus
  9. “Verilog-AMS Language Reference Manual,” August 2008, http://www.designers-guide.org/VerilogAMS/.
  10. A. L. Fetter, “Electrodynamics of a layered electron gas. I. Single layer,” Annals of Physics, vol. 81, no. 2, pp. 367–393, 1973. View at Scopus
  11. A. L. Fetter, “Electrodynamics of a layered electron gas. II. Periodic array,” Annals of Physics, vol. 88, no. 1, pp. 1–25, 1974. View at Scopus
  12. A. Maffucci, G. Miano, and F. Villone, “A transmission line model for metallic carbon nanotube interconnects,” International Journal of Circuit Theory and Applications, vol. 36, no. 1, pp. 31–51, 2008. View at Publisher · View at Google Scholar · View at Scopus
  13. Y. Xu and A. Srivastava, “A model for carbon nanotube interconnects,” International Journal of Circuit Theory and Applications, pp. 1–17, 2009, Published online in Wiley InterScience (http://www3.interscience.wiley.com/). View at Publisher · View at Google Scholar
  14. D. T. Thomas, Engineering Electromagnetics, Pergamon Press, New York, NY, USA, 1972.
  15. T. A. Fjeldly, T. Ytterdal, and M. S. Shur, Introduction to Device Modeling and Circuit Simulation, Wiley, New York, NY, USA, 1998.
  16. Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User's Guide, Springer, New York, NY, USA, 1999.
  17. B. Streetman and S. Banerjee, Solid State Electronic Devices, Prentice Hall, Upper Saddle River, NJ, USA, 5th edition, 2000.
  18. S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, “Fabrication and electrical characterization of top gate single-wall carbon nanotube field-effect transistors,” Journal of Vacuum Science and Technology B, vol. 20, no. 6, pp. 2798–2801, 2002. View at Publisher · View at Google Scholar · View at Scopus
  19. M. P. A. Fisher and L. I. Glazman, “Transport in a one-dimensional Lüttinger liquid,” in Mesoscopic Electron Transport, L. Kouwenhoven, G. Schoen, and L. Sohn, Eds., vol. 345 of NATO ASI Series E, pp. 331–373, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1996.
  20. S. Ramo, J. R. Whinnery, and T. V. Duzer, Fields and Waves in Communication Electronics, Wiley, New York, NY, USA, 1994.
  21. A. Thess, R. Lee, P. Nikolaev, et al., “Crystalline ropes of metallic carbon nanotubes,” Science, vol. 273, no. 5274, pp. 483–487, 1996. View at Scopus
  22. Ph. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, “Carbon nanotube electronics,” Proceedings of the IEEE, vol. 91, no. 11, pp. 1772–1783, 2003. View at Publisher · View at Google Scholar · View at Scopus
  23. M. Liebau, A. P. Graham, G. S. Duesberge, E. Unger, R. Seidel, and F. Kreupl, “Nanoelectronics based on carbon nanotubes: technological challenges and recent developments,” Fullerenes Nanotubes and Carbon Nanostructures, vol. 13, no. S1, pp. 255–258, 2005. View at Publisher · View at Google Scholar · View at Scopus
  24. N. Peng, Q. Zhang, J. Li, and N. Liu, “Influences of ac electric field on the spatial distribution of carbon nanotubes formed between electrodes,” Journal of Applied Physics, vol. 100, no. 2, Article ID 024309, 5 pages, 2006. View at Publisher · View at Google Scholar · View at Scopus
  25. M. Zheng, A. Jagota, M. S. Strano, et al., “Structure-based carbon nanotube sorting by sequence-dependent DNA assembly,” Science, vol. 302, no. 5650, pp. 1545–1548, 2003. View at Publisher · View at Google Scholar · View at PubMed · View at Scopus
  26. D. M. Rosenthal and R. M. Asimow, Introduction to Properties of Materials, Van Nostrand Reinhold, New York, NY, USA, 1971.
  27. Y. Bin, W. Haihong, A. Joshi, X. Qi, I. Effiong, and L. Ming-Ren, “15 nm gate length planar CMOS transistor,” in Proceedings of IEEE International Electron Devices Meeting (IEDM '01), pp. 11.7.1–11.7.3, Washington, DC, USA, 2001. View at Publisher · View at Google Scholar
  28. R. Chau, J. Kavalieros, B. Doyle, et al., “A 50 nm depleted-substrate CMOS transistor (DST),” in Proceedings of IEEE International Electron Devices Meeting (IEDM '01), pp. 29.1.1–29.1.4, Washington, DC, USA, 2001. View at Publisher · View at Google Scholar
  29. Z. Chen, J. Appenzeller, P. M. Solomon, Y.-M. Lin, and Ph. Avouris, “High performance carbon nanotube ring oscillator,” in Proceedings of the 64th Device Research Conference, pp. 171–172, State College, Pa, USA, June 2006. View at Publisher · View at Google Scholar
  30. P. J. Burke, “Lüttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes,” IEEE Transactions on Nanotechnology, vol. 1, no. 3, pp. 129–144, 2002. View at Publisher · View at Google Scholar · View at Scopus
  31. Y. Massoud and A. Nieuwoudt, “Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits,” Journal on Emerging Technologies in Computing Systems, vol. 2, no. 3, pp. 155–196, 2006. View at Publisher · View at Google Scholar · View at Scopus
  32. A. Nieuwoudt and Y. Massoud, “On the optimal design, performance, and reliability of future carbon nanotube-based interconnect solutions,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2097–2110, 2008. View at Publisher · View at Google Scholar · View at Scopus
  33. P. L. McEuen, M. S. Fuhrer, and H. Park, “Single-walled carbon nanotube electronics,” IEEE Transactions on Nanotechnology, vol. 1, no. 1, pp. 78–85, 2002. View at Publisher · View at Google Scholar · View at Scopus
  34. “International Technology Roadmap for Semiconductors,” 2007, http://www.itrs.net/Links/2007ITRS/Home2007.htm.
  35. A. Nieuwoudt and Y. Massoud, “On the impact of process variations for carbon nanotube bundles for VLSI interconnect,” IEEE Transactions on Electron Devices, vol. 54, no. 3, pp. 446–455, 2007. View at Publisher · View at Google Scholar · View at Scopus