A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Table 3

Data Widths and latencies of CalcDist.

Signal/Core	Data Widths	Latency
Input	32-bit (signed 12.20)	—
Subtractor	32-bit i/p, 33-bit o/p	1
Multiplier	33-bit i/p, 66-bit o/p	7
Adder1	65-bit i/p, 66-bit o/p	1
Adder2	66-bit i/p, 67-bit o/p	1
Output	53-bit (unsigned 27.26)	—