A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Figure 17

Lock-in process of the proposed ADPLL. (a) Lock process of the ADPLL with five different kinds of status from “000” status to “100” status. (b) Frequency acquisition at $T_{\text{DCO}}=T_{\text{Ref}}$ during “000” status, (c) Frequency acquisition at $T_{\text{DCO}}=T_{\text{ref}}-T_{\text{delay}}$ during “010” status_, (d) Phase acquisition process during “011” status.

(a)

(b)

(c)

(d)