Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

<table>Drain current for conventional bulk devices and localized halo ISE devices [<a href="/journals/vlsi/2011/178516/#B29">35</a>].</table>

VLSI Design

Figure 30: Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications 