Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Table 3

Roadmap for deep submicron CMOS devices.

Range of
operation
Performance factorsChallengesTechnique/SolutionEnhanced performanceApplications

Sub-50 nmLoss of drive current and enhancement in SCEVoltage scaling limitation, 𝑉 t h scalingNonuniform doping profile (SSR)
Lateral channel engineering
High linear current 50 mV drain bias, exhibit smaller roll-off, currents less than UD devicesHP [26]

Sub-50 nmRevere-biased diode junc. BTBT currentReduce BTBTReduce peak halo doping conc.
Asymmetric halo (AH) doping
Dissipates less static power in circuits, improvement in performanceLOP-LSTP [32]

Sub-50 nmLarge variation in different leakage components due to variation in device parameters 𝑉 t h variability, due to random dopant fluctuation and junction capacitanceIncrease in strength of halo
Modified AH halo
Min jn. BTBT and highest performance for a given subthreshold leakage, reduces subthreshold leakage, improves SCELOP [26]

Sub-50 nmAdverse 𝑉 t h roll-offDIBLHigh halo doping on source side
Non uniform doping
𝑉 t h drop as a result of DIBL effect is reducedLOP [32]

Sub-50 nmRoll off of short channel 𝑉 t h and gate/drain leakageBTBT control, 𝑉 t h roll-offHalo to extension spacing
Implant localized halo beneath the channel surface
Sub-50-nm bulk MOSFET devices can be achieved with small 𝑉 t h roll-off, low DIBL, suitable 𝑉 t h LOP [35]

Sub-50 nmNet doping conc. decreases laterally with a slope of 4-5 nm/dec, difficult to use superhalo tech. for PMOSAcceptable short channel effectsLat. conc. dis. of B, Ar, p+ optimized poly-Si gate
Lateral net doping profile in SALVO design
Produces PMOS devices with lateral net doping slope as abrupt as 6 nm/dec for a metal gate, 8.5 nm/dec for a poly Si gate down to 25 nm 𝐿 g LSTP [29]

Sub-22 nmMetal gate work function affects 𝑉 t h of device and tuning and power of digital circuitsIntrinsic parameter fluctuationsMetal gate technology
High-k dielectrics
Intrinsic parameter fluctuations controlledHP-LOP [24]

Sub-22 nmProcess variation effects, random dopant fluctuation affects 𝑉 t h of deviceIntrinsic parameter fluctuationRandom variation of work function
Metal gate technology
Metal as a gate material introduces a new source of random variation due to the dependence of work functions on the orientation of metal grainsHP-LSTP [24]