Table 8: Chip layout specification (mode-4 prediction).

Inputs/Outputs13/2
Technology0.18 μm CMOS
Die dimension ( 𝑊 × 𝐻 ) 1 . 6 m m × 1 . 6 m m
Core dimention ( 𝑊 × 𝐻 ) 1 m m × 1 m m
Number of cells24 K1
Latency1 clock cycle
Max DCLK frequency42 MHz
Core power consumption1.78 mW2@ fps = 2

1,2Including the buffer memory to store one row of images for 𝑌 , 𝑈 , and 𝑉 components.