VLSI Design

Research Article

CONTANGO: Integrated Optimization of SoC Clock Networks

Algorithm 1

Iterative wiresizing.
𝑇 w s = T w s E s t i m a t i o n ( ) ;
repeat
 SaveSolution(); ComputeWireSlacks();
  𝑄 = { r o o t } ; 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ = { 0 } ; 𝑖 = 0 ;
 while   𝑖 < 𝑠 𝑖 𝑧 𝑒 ( 𝑄 )   do
  If ( 𝑆 𝑙 π‘Ž 𝑐 π‘˜ [ 𝑄 𝑖 ] βˆ’ 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ 𝑖 > 𝑇 w s ) then
    π‘˜ = ( 𝑆 𝑙 π‘Ž 𝑐 π‘˜ [ 𝑄 𝑖 ] βˆ’ 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ 𝑖 ) / 𝑇 w s ;
   DownSize( π‘Š 𝑖 π‘Ÿ 𝑒 [ 𝑄 𝑖 ] , π‘˜ ); 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ 𝑖 + = π‘˜ 𝑇 w s ;
  end  if
  for   𝑗 = 1 to Size( 𝐢 β„Ž 𝑖 𝑙 𝑑 [ 𝑄 𝑖 ] ) do
    𝑄 .push( 𝐢 β„Ž 𝑖 𝑙 𝑑 [ 𝑄 𝑖 ] [ 𝑗 ] ); 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ .push( 𝑅 𝑆 𝑙 π‘Ž 𝑐 π‘˜ 𝑖 );
  end  for
   + + 𝑖 ;
 end  while
 SpiceSimulation();
until (no improvement β€– slew violation)