Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2011
/
Article
/
Fig 1
/
Research Article
CONTANGO: Integrated Optimization of SoC Clock Networks
Figure 1
Min-wirelength trees with zero and bounded skew (Elmore delay). Only fragments of actual clock trees are shown.
(a)
ZST
(b)
3 ps BST
(c)
9 ps BST