CONTANGO: Integrated Optimization of SoC Clock Networks

Figure 4

The clock tree produced by Contango on ispd09 fnb1. Sinks are indicated by crosses, buffers are indicated by blue rectangles. L-shapes are drawn as “diagonal wires” to reduce clutter. Wires are colored by a red-green gradient to reflect slowdown slacks, as described in Section 3.2. The impact of wiresnaking is too small to be visible.