Research Article

CONTANGO: Integrated Optimization of SoC Clock Networks

Table 3

Progress achieved by individual steps of Contango on ISPD’09 benchmarks: the first letter in each acronym indicates top-down (T) or bottom-level (B) optimization, second letter differentiates wires (W) from buffers (B), while “Sz” stands for “sizing” and “Sn” stands for “snaking”. Italic numbers indicate whether skew or CLR was the primary optimization objective.

ISPD09F11 ISPD09F12 ISPD09F21 ISPD09F22 ISPD09F31 ISPD09F32 ISPD09FNB1
CLRSkewCLRSkewCLRSkewCLRSkewCLRSkewCLRSkewCLRSkew

Initial56.18 30.5875.8148.9689.2959.1752.0131.55151.8116.5121.688.1931.8621.15
TBSz55.61 46.7880.0366.2489.4976.3143.1633.65140.3129.2110.798.2731.5421.13
TWSz23.38 15.0719.70 8.12726.00 12.2516.35 6.93343.08 32.2127.23 14.8430.75 20.44
TWSn13.75 2.92916.21 3.38417.60 2.82612.58 1.9912.81 3.9117.92 4.59413.94 3.149
BWSn 13.36 2.867 15.27 2.611 17.40 2.738 12.36 2.227 12.81 3.91 17.92 4.594 13.40 3.5