The Impact of Statistical Leakage Models on Design Yield Estimation
Figure 2
The accesses cell is storing a “0”. The read bitline (RBL) should stay high. Leakage from unaccessed cells can falsely discharge the bitline. Leakage can happen due to (a) all the cells on the bitline leaking, or (b) an intermediate number of cells leaking. For our work, we ignore the stack leakages if both read transistors (whose gates are the cell and RWL) are OFF.
