A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="475952.fig.009a" src="https://static.hindawi.com/articles/vlsi/volume-2011/475952/figures/475952.fig.009a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Voltage sensing configuration of the interface electronics for MEMS capacitive sensor</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="475952.fig.009b" src="https://static.hindawi.com/articles/vlsi/volume-2011/475952/figures/475952.fig.009b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>OTA-C realizations of amplifier and filter</td></tr></table></td></tr></table>

<table>Considered system for experiment 3.</table>

VLSI Design

fig9

Figure 9

Figure 9: A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies 