A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

<table class="table-group" id="tab13"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td align="left">Performances</td><td align="center"> Pred</td><td align="center"> SPICE</td><td align="center"> Error <svg height="11.45" id="M259" style="vertical-align:-0.23825pt" version="1.1" viewbox="0 0 11.8 11.45" width="11.8" xmlns="http://www.w3.org/2000/svg">
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</svg></td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td align="left">Noise (nV<svg height="20.4125" id="M260" style="vertical-align:-2.64594pt" version="1.1" viewbox="0 0 37.200001 20.4125" width="37.200001" xmlns="http://www.w3.org/2000/svg">
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</svg>)</td><td align="center"> 19.65</td><td align="center"> 20.32</td><td align="center"> 3.40</td></tr><tr><td align="left"> Power (<i>μ</i>W)</td><td align="center"> 572.78</td><td align="center"> 592</td><td align="center"> 3.36</td></tr><tr><td align="left"> Parasitics (fF)</td><td align="center"> 92.05</td><td align="center"> 94.12</td><td align="center"> 2.24</td></tr><tr><td align="left"> Sensitivity</td><td align="center"> 145.16</td><td align="center"> 138</td><td align="center"> 4.93</td></tr><tr><td align="left"> Cutoff (KHz)</td><td align="center"> 35.28</td><td align="center"> 38</td><td align="center"> 7.70</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Comparison of predicted performances and SPICE value.

VLSI Design

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Table 13

Table 13: A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies 