VLSI Design

Research Article

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Table 2

Transistor sizes and feasibility constraints for OTA.
Parameters Ranges
Transistor sizes
Geometry constraints		 𝑊 1 = 𝑊 2 ( 2 8 0 n m , 4 0 0 𝜇 m )
𝑊 3 = 𝑊 4 = 𝑊 6 = 𝑊 7 ( 1 𝜇 m , 2 0 𝜇 m )
𝑊 8 = 𝑊 9 ( 2 8 0 n m , 1 0 𝜇 m )
𝑊 5 ( 1 𝜇 m , 5 0 𝜇 m )
𝑊 1 0 = 𝑊 1 1 ( 2 8 0 n m , 4 0 0 𝜇 m )
𝐶 𝐿 ( 1 p F , 1 0 p F )
Parameters Range
Functional constraints 𝑉 g s − 𝑉 t h ≥0.1 V
𝑉 o p ≈ 0.9 V
𝑉 o f f ≤2 mV
Slew rate ( 0 . 1 V / 𝜇 s , 2 0 V / 𝜇 s )
Performance constraints Bandwidth ≥2 MHz
DC gain ≥70 dB
Phase margin ( 4 5 ∘ , 6 0 ∘ )