Shedding Physical Synthesis Area Bloat

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="503025.fig.007a" src="https://static.hindawi.com/articles/vlsi/volume-2011/503025/figures/503025.fig.007a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>a simple physical synthesis flow</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="503025.fig.007b" src="https://static.hindawi.com/articles/vlsi/volume-2011/503025/figures/503025.fig.007b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>detail steps of optimization</td></tr></table></td></tr></table>

VLSI Design

fig7

Figure 7

Figure 7: Shedding Physical Synthesis Area Bloat 