Buffer Planning for IP Placement Using Sliced-LFF

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="530851.fig.0010a" src="https://static.hindawi.com/articles/vlsi/volume-2011/530851/figures/530851.fig.0010a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Larger FR</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="530851.fig.0010b" src="https://static.hindawi.com/articles/vlsi/volume-2011/530851/figures/530851.fig.0010b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Smaller FR</td></tr></table></td></tr></table>

VLSI Design

fig10

Figure 10

Figure 10: Buffer Planning for IP Placement Using Sliced-LFF 